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lt3513 1 3513fc typical a pplica t ion descrip t ion fea t ures a pplica t ions 2mhz high current 5-output regulator for tft-lcd panels the lt ? 3513 5-output adjustable switching regulator provides power for large tft-lcd panels. the 38-pin 5mm 7mm qfn device can generate a 3.3v or 5v logic supply along with the triple output supply required for the tft-lcd panel. a lower voltage secondary logic supply may also be generated with the addition of an external npn driven by the internal linear regulator. a step-down regulator provides a low voltage output, v logic , with up to 1.2a of current while capable of operating from a wide input range of 4.5v to 30v. a high power step-up con - verter, a lower power step-up converter and an inverting converter provide the three independent output voltages: av dd , v on and v off required by the lcd panel. a high-side pnp provides delayed turn-on of the v on signal and can handle up to 30ma. protection circuitry ensures that v on is disabled if any of the four outputs are more than 10% below the programmed voltage. n automotive tft -lcd displays n large tft-lcd desktop monitors n flat panel televisions n 4.5v to 30v input voltage range n four integrated switches: 2.2a buck, 1.5a boost, 0.25a boost, 0.25a inverter (guaranteed minimum current limit) n external npn ldo driver n fixed frequency, low noise outputs n inductor current sense for buck n soft-start for all outputs n externally programmable v on delay n three integrated schottky diodes n pgood pin for a v dd output disconnect n panelprotect? circuitr y disables v on upon fault n thermally enhanced 38-lead 5mm 7mm qfn package start-up waveforms av dd 10v/div run/ss 2v/div v logic 5v/div i in(avg) 1a/div v off 10v/div v e3 20v/div v on 20v/div 5ms/div 3513 ta01b l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and panelprotect, true color pwm and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. v c1 7.5k 4.7k 2.7nf 4.7nf 10f v ldo 3.3v 0.5a v logic 5v 0.5a v off ?10v 20ma v in 8v to 16v 22f 4.7h 0.22f 47nf 15nf 15nf 15nf v on 22v 20ma 2.2f v c3 30k 165k 232k 10k 1.5nf v c2 v c1 gnd 13k 2.2nf v c4 v in v logic 5v ldopwr lt3513 uvlo sw2 2.2f fb5 fb3 bd fb1 sense ? sense + sw1 boost bias sw3 6.8h 42.2k 10k 30.1k 10k 69.8k 10h 0.47f 10k 60.4k 178k 53.6k 100k 10k 10f 10h av dd 8v 80ma 10f 0.47f nfb4 d4 sw4 run-ss3/4 c t run-ss2 run-ss1 v onsink e3 v on v on_clk v on_clk pgood fb2 v logic 5v 3513 ta01a
lt3513 2 3513fc (note 1) v in , ldopwr voltage ............................................... 32 v uvlo voltage ............................................................ 32 v sw2, sw3, sw4 voltage .......................................... 4 0v e3 pin voltage ........................................................... 4 0v v on , v onsink voltage ................................................ 4 0v pgood voltage ......................................................... 4 0v d4 voltage ........................................................ 1 v, C 4 0 v boost voltage ......................................................... 37 v boost over sw1 ....................................................... 8v se nse + , sense C voltage .......................................... 10 v v on_clk voltage ........................................................ 10 v bias, bd voltage ...................................................... 10 v c t pin voltage ............................................................. 5v run -ss1, run-ss2, run-ss3/4 voltage ................... 5v f b1, fb2, fb3, fb5 voltage ......................................... 5v nf b4 voltage ...................................................... 5v , C5v v c1 , v c2 , v c3 , v c4 voltage .......................................... 5v jun ction temperature (note 8) ............................. 1 25c operating temperature range (note 2).. C40c to 125c storage temperature range .................. C 65c to 125c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, bias = 3v, unless otherwise noted. parameter conditions min typ max units minimum input voltage l 4.5 v quiescent current not switching v runss1 = 0v 7.5 30 12 65 ma a run-ss1, run-ss2, run-ss3/4 pin current run-ss1= run-ss2 = run-ss3 = run-ss4 = 0.4v 2 a run-ss1, run-ss2, run-ss3/4 threshold 0.8 v bias pin voltage to begin run-ss2, run-ss3/4 l 2.25 2.7 v bias pin current bias = 3.1v, all switches off 16.5 20 ma p in c on f igura t ion 13 14 15 16 top view 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1fb5 v c1 run-ss3/4 fb3 run-ss2 sw3 e3 v on v onsink v on_clk pgood v c3 sense + sense ? bias boost ldopwr bd sw4 d4 nfb4 run-ss1 v c4 v c2 uvlo v in v in sw1 sw1 gnd fb1 c t gnd sw2 sw2 gnd bias fb2 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w, jc = 1c/w exposed pad (pin 39) is gnd, must be soldered to pcb o r d er i n f orma t ion lead free finish tape and reel part marking* package description temperature range lt3513euhf#pbf lt3513euhf#trpbf 3513 38-lead (5mm 7mm) plastic qfn C40c to 125c lt3513iuhf#pbf lt3513iuhf#trpbf 3513 38-lead (5mm 7mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ a bsolu t e m aximum r a t ings e lec t rical c harac t eris t ics
lt3513 3 3513fc e lec t rical c harac t eris t ics parameter conditions min typ max units fb threshold offset to begin c t charge (note 3) 90 125 160 mv c t pin current source all fb pins = 1.5v, c t = 0.35v 16 20 25 a c t threshold to power v on all fb pins = 1.5v 1 1.1 1.2 v v on switch drop v on current = 30ma 200 400 mv maximum v on current v e3 = 30v l 30 50 ma v on_clk input voltage high 1.5 v v on_clk input voltage low 0.3 v v onsink voltage on v onsink current = 1a l 1.2 v master oscillator frequency l 1.90 1.80 2 2.12 2.22 mhz mhz foldback switching frequency fb2 = 0v, fb3 = 0v, nfb4 = 0v 200 khz uvlo pin threshold uvlo pin voltage rising 1.25 v uvlo pin hysteresis current v uvlo = 1v 3.4 3.9 4.5 a pgood threshold offset 90 125 160 mv pgood sink current pgood connected to 40v through 100k 4 ma pgood pin leakage v pgood = 40v 1 a switch 1 (2.2a buck) fb1 voltage l 1.215 1.205 1.235 1.255 1.265 v v fb1 voltage line regulation 4.5v < v in < 30v 0.01 0.03 %/v fb1 pin bias current (note 4) l 30 200 na error amplifier 1 voltage gain 250 v/v error amplifier 1 transconductance )i = 10a 220 mhos maximum duty cycle l 75 85 % switch 1 current limit duty cycle = 35% (note 6) 2.2 3 3.5 a switch 1 v cesat i sw = 1.5a 430 mv switch 1 leakage current fb1 = 1.5v, run-ss1 = 0v 0.1 10 a minimum boost voltage above sw1 pin i sw = 1.5a (note 7) 1.8 2.5 v boost pin current i sw = 1.5a 30 50 ma boost schottky diode drop i = 170ma 700 mv switch 2 (1.5a boost) fb2 voltage l 1.20 1.19 1.22 1.24 1.25 v v fb2 voltage line regulation 4.5v < v in < 30v 0.01 0.03 %/v fb2 pin bias current (note 5) l 30 200 na error amplifier 2 voltage gain 250 v/v error amplifier 2 transconductance )i = 10a 220 mhos switch 2 current limit (note 6) 1.5 1.85 2.4 a switch 2 v cesat i sw2 = 1.2a 360 mv switch 2 leakage current fb2 = 1.5v, run-ss1 = 0v 0.1 1 a bias pin current due to sw2 i sw2 = 1.2a 45 ma maximum duty cycle (sw2) l 75 90 % the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, bias = 3v, unless otherwise noted.
lt3513 4 3513fc parameter conditions min typ max units switch 3 (250ma boost) fb3 voltage l 1.20 1.19 1.22 1.24 1.25 v v fb3 voltage line regulation 4.5v < v in < 30v 0.01 0.03 %/v fb3 pin bias current (note 4) l 30 200 na error amplifier 3 voltage gain 250 v/v error amplifier 3 transconductance )i = 10a 220 mhos switch 3 current limit (note 6) 0.25 0.3 0.38 a switch 3 v cesat i sw3 = 0.2a 200 mv switch 3 leakage current fb3 = 1.5v, run-ss1 = 0v 0.1 1 a bias pin current due to sw3 i sw3 = 0.2a 18 ma maximum duty cycle (sw3) l 84 88 % schottky diode drop i = 170ma 900 mv switch 4 (250ma inverter) nfb4 voltage l C1.205 C1.215 C1.180 C1.155 C1.145 v v nfb4 voltage line regulation 4.5v < v in < 30v 0.01 0.03 %/v nfb4 pin bias current (note 4) l 5 16 a error amplifier 4 voltage gain 200 v/v error amplifier 4 transconductance )i = 10a 220 mhos switch 4 current limit (note 6) 0.25 0.3 0.40 a switch 4 v cesat i sw4 = 0.2a 200 mv switch 4 leakage current nfb4 = C1.5v, run-ss1 = 0v 0.1 1 a bias pin current due to sw4 i sw4 = 0.2a 18 ma maximum duty cycle (sw4) 84 88 % schottky diode drop (d4) i = 170ma 700 mv npn ldo fb5 voltage l 0.61 0.6 0.625 0.63 0.65 v v fb5 pin bias current (note 4) l 30 200 na base drive current fb5 = 0.5v 6 8 10 ma ldopwr minimum voltage bd = 3.5v 4.5 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3513e is guaranteed to meet specified performance from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3513i is guarenteed over the full C40c to 125c operating junction temperature range. note 3: the c t pin is held low until fb1, fb2, fb3 and nfb4 all ramp above the fb threshold offset. note 4: current flows out of fb1, fb3, nfb4 and fb5. note 5: current may flow in or out of fb2. the absolute value of this test is used. note 6: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 7: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature range when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, bias = 3v, unless otherwise noted. e lec t rical c harac t eris t ics
lt3513 5 3513fc typical p er f ormance c harac t eris t ics maximum output current for v logic = 3.3v sw1 current limit vs duty cycle start and run v logic = 3.3v boost pin current sw2 current limit sw3 current limit sw4 current limit sw1 v cesat sw2 v cesat v in (v) 0 2.0 2.2 2.6 15 3513 g01 1.8 1.6 5 10 20 1.4 1.2 2.4 i out(max) (a) l = 2.4h l = 4.3h duty cycle (%) 25 0 sw1 current limit (a) 0.5 1.0 1.5 2.0 2.5 3.0 35 45 55 65 3513 g02 75 sw1 current limit vs duty cycle minimum load current (a) 0.001 4 v in (v) 6 8 0.01 0.1 1 3513 g03 2 3 5 7 1 0 v in(min) start v in(min) run switch current (ma) 0 70 60 50 40 30 20 10 0 1500 2500 3513 g04 500 1000 2000 3000 boost current (ma) ambient temperature (c) ?40 1.5 sw current limit (a) 1.6 1.8 1.9 2.0 2.5 2.2 10 60 85 3513 g05 1.7 2.3 2.4 2.1 ?15 35 110 ambient temperature (c) ?50 sw current limit (ma) 300 350 400 110 3513 g06 250 200 100 ?10 30 70 ?30 10 50 90 150 500 450 ambient temperature (c) ?50 sw current limit (ma) 300 350 400 110 3513 g07 250 200 100 ?10 30 70 ?30 10 50 90 150 500 450 sw1 current (ma) 0 0 v cesat (mv) 200 400 600 500 1000 1500 2000 3513 g08 2500 800 1000 100 300 500 700 900 3000 i sw2 (ma) 0 v ce2sat (mv) 200 400 600 100 300 500 400 800 1200 1600 3513 g09 2000 0 t a = 25c, unless otherwise noted.
lt3513 6 3513fc typical p er f ormance c harac t eris t ics sw3 v cesat sw4 v cesat v on current limit oscillator frequency frequency foldback reference voltage i sw3 (ma) 0 v ce3sat (mv) 200 250 300 150 250 3513 g10 150 100 50 100 200 300 350 50 0 i sw (ma) 0 200 250 350 150 250 3513 g11 150 100 50 100 200 300 350 50 0 300 v cesat (mv) v e3 (v) 0 0 i on limit (ma) 5 15 20 25 20 45 3513 g12 10 10 5 25 30 15 35 30 35 40 ambient temperature (c) ?50 frequency (mhz) 2.1 2.2 2.3 3513 g13 2.0 1.9 1.7 0 50 100 1.8 2.5 2.4 v fb (mv) 0 switching frequency (khz) 1500 2000 2500 450 750 1200 3513 g14 1000 500 0 150 300 600 900 1050 temperature (c) ?40 ?15 1.20 reference voltage (v) 1.22 1.25 10 60 85 3513 g15 1.21 1.24 1.23 35 110 t a = 25c, unless otherwise noted.
lt3513 7 3513fc bias pin current efficiency, av dd = 13v efficiency, v logic = 5v temperature (c) ?50 0 bias current (ma) 10 20 30 40 50 60 0 50 100 150 3513 g16 l2 = 10h l3 = 10h l4 = 10h i sw2 = 0a i sw3 = 0a i sw4 = 0a load current (ma) 1 40 efficiency (%) 50 60 70 80 90 100 100 200 300 400 3513 g17 500 i out (ma) 100 efficiency (%) 70 80 90 100 700 1100 3513 g18 60 50 300 500 900 1300 1500 40 typical p er f ormance c harac t eris t ics ldo current limit vs temperature v uvlo vs temperature reference voltage for fb5, ldo ambient temperature (c) ?50 0 base current limit of internal pnp (ma) 1 3 4 5 50 9 3513 g19 2 0 ?25 75 100 25 125 6 7 8 ambient temperature (c) ?50 1.30 1.31 1.33 100 3513 g20 1.29 1.28 0 50 1.27 1.26 1.32 uvlo (v) uvlo for start uvlo minimum for run temperature (c) ?40 640 650 670 35 85 3513 g21 630 620 ?15 10 60 110 610 600 660 reference voltage (mv) t a = 25c, unless otherwise noted.
lt3513 8 3513fc fb5 (pin 1): feedback pin. tie the resistor tap to this pin and set the output of the ldo according to v ldo = 0.625 ? (1 + r14/r15). reference designators refer to figure 1. v c1 (pin 2): control voltage and compensation pin for internal error amplifier. connect a series rc from this pin to ground to compensate switching regulator 1. run-ss3/4 (pin 3): run/soft-start pin. this is the soft- start pin for switching regulators 3 and 4. place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. when the bias pin reaches 2.25v, a 2a current source charges the capacitor. when the voltage at this pin reaches 0.8v, switches 3 and 4 turn on and begin switching. for slower start-up use a larger capacitor. for complete shutdown tie run-ss3/4 to ground. fb3 (pin 4): feedback pin. tie the resistor tap to this pin and set v on according to v on = 1.22v ? (1 + r8/r9) C 150mv. reference designators refer to figure 1. run-ss2 (pin 5): run/soft-start pin. this is the soft-start pin for switching regulator 2. place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. when the bias pin reaches 2.25v, a 2a cur - rent source charges the capacitor. when the voltage at this pin reaches 0.8v, switch 2 turns on and begins switching. for slower start-up use a larger capacitor. for complete shutdown tie run-ss2 to ground. sw3 (pin 6): switch node. the sw3 pin is the collector of the internal npn bipolar transistor for switching regulator 3. minimize trace area at this pin to keep emi down. e3 (pin 7): this is switching regulator 3s output and the emitter of the output disconnect pnp. tie the output capacitor and resistor divider here. v on (pin 8): this is the delayed output for switching regulator 3. v on reaches its programmed voltage after the internal c t timer times out. protection circuitry ensures v on is disabled if any of the four outputs are more than 10% below normal voltage. this output is also disabled when v on_clk is high. v onsink (pin 9): this is an open-collector output controlled by the v on_clk pin. when v on_clk is low, this pin draws no current and when v on_clk is high, this pin draws current. v on_clk (pin 10): this pin controls the output disconnect device and the open collector of v onsink . when this pin is low, the v on pin is enabled and the v onsink pin is a high impedance. when this pin is high, the v on pin is disabled and the v onsink pin sinks current to ground. pgood (pin 11): power good comparator output. this is the open collector output of the power good comparator and can be used in conjunction with an external p-channel mosfet to provide output disconnect for av dd as shown in figure 2. when switcher 2s output reaches approximately 90% of its programmed voltage, pgood will be pulled to ground. this will pull down on the gate of the mosfet, connecting av dd . a 100k pull-up resistor between the source and the gate of the p-channel mosfet keeps it off when switcher 2s output is low. v c3 (pin 12): control voltage and compensation pin for internal error amplifier. connect a series rc from this pin to ground to compensate switching regulator 3. c t (pin 13): timing capacitor pin. this is the input to the v on timer and programs the time delay from all four feedback pins reaching 1.125v to v on turning on. the c t capacitor value can be set using the equation c = (20a ? t delay )/1.1v. gnd (pins 14, 17, 33): ground. sw2 (pins 15, 16): switch node. the sw2 pin is the col- lector of the internal npn bipolar transistor for switching regulator 2. minimize trace area at this pin to keep emi down. bias (pins 18, 29): the bias pin is used to improve effi- ciency when operating at higher input voltages. connecting this pin to the output of switching regulator 1 forces most of the internal circuitry to draw its operating current from v logic rather than v in . the drivers of switches 2, 3 and 4 and the ldo are supplied by bias. switches 2, 3 and 4 and the ldo will not function until the bias pin reaches approximately 2.7v. both bias pins must be tied to v logic . fb2 (pin 19): feedback pin. tie the resistor divider tap to this pin and set av dd according to av dd = 1.22v ? (1 + r5/r6). reference designators refer to figure 2. p in func t ions
lt3513 9 3513fc v c2 (pin 20): control voltage and compensation pin for internal error amplifier. connect a series rc from this pin to ground to compensate switching regulator 2. v c4 (pin 21): control voltage and compensation pin for internal error amplifier. connect a series rc from this pin to ground to compensate switching regulator 4. run-ss1 (pin 22): run/soft-start pin. this is the soft-start pin for switching regulator 1. place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. when power is applied to the v in pin, a 2a current source charges the capacitor. when the voltage at this pin reaches 0.8v, switch 1 turns on and begins switching. for slower start-up use a larger capacitor. for complete shutdown tie run-ss1 to ground. nfb4 (pin 23): negative feedback pin. tie the resistor di- vider tap to this pin and set v off according to v off = C1.18 ? (1 + r3/r4). reference designators refer to figure 2. d4 (pin 24): internal schottky diode pin. this pin is the anode of an internal schottky diode with the other end connected to ground. this schottky diode is used in generating the v off output. sw4 (pin 25): switch node. the sw4 pin is the collector of the internal npn bipolar transistor for switching regulator 4. minimize trace area at this pin to keep emi down. bd (note 26): npn ldo base drive. this pin controls the base of the external npn ldo transistor. ldopwr (pin 27): input voltage for ldo driver. this pin supplies the current for the npn ldo base. this pin can be connected to v in . to save power at high v in voltages, the pin can alternatively be connected to the av dd supply. boost (pin 28): the boost pin is used to provide a drive voltage higher than v in to the switch 1 drive circuit. an internal schottky diode is connected between bias and boost. a capacitor needs to be connected between boost and sw1. sense C (pin 30) negative current sense input. this pin (along with the sense + pin) is used to sense the inductor current for the buck switching regulator. sense + (pin 31) positive current sense input. this pin (along with the sense C pin) is used to sense the inductor current for the buck switching regulator. fb1 (pin 32): feedback pin. tie the resistor divider tap to this pin and set v logic according to v logic = 1.235v ? (1 + r1/r2). reference designators refer to figure 2. sw1 (pins 34, 35): switch node. the sw1 pins are the emitter of the internal npn bipolar power transistor for switching regulator 1. these points must be tied together for proper operation. connect these pins to the inductor, catch diode and boost capacitor. v in (pins 36, 37): input voltage. this pin supplies current to the internal circuitry of the lt3513. this pin must be locally bypassed with a capacitor. uvlo (pin 38): undervoltage lockout. a resistor divider connected to v in is tied to this pin to program the minimum input voltage at which the lt3513 will operate. this pin is compared to the internal 1.25v reference. when uvlo is less than 1.25v, the switching regulators are not allowed to operate (the run/ss pins are still used to turn on each switching regulator). when this pin falls below 1.25v, 3.9a will be pulled from the pin to provide programmable hysteresis for uvlo. exposed pad (pin 39): ground. the exposed pad of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the exposed pad must be soldered to the circuit board for proper operation. p in func t ions
lt3513 10 3513fc 6 12 + ? + ? + s q 1.22v g m 1.18v 1.22v 1.1v 1.235v r driver bias v c3 sw3 9 v onsink 10 v on_clk v on_clk 7 e3 3513 f01 foldback oscillator 25 21 + ? + ? + ? + ? + ? + s q r driver bias v c4 23 nfb4 100k 100k sw4 24 d4 foldback oscillator 20 + ? + ? + 1.1v fb2 + + s q r driver v c2 30 sense ? 31 28 sense + sw2 15, 16 bias 18, 29 foldback oscillator g m g m 2 + ? + ? + s q r driver bias current sense amp v c1 sw1 34, 35 boost v in slope comp/ one-shot g m g m ? ? ? ? + 13 c t 22 run-ss1 3 run-ss3/4 bias 38 uvlo 11 pgood uvlo 1.25v 3.9a 2a 2a 20a 19 fb2 32 fb1 bd 1 fb5 ldopwr gnd 14,17,33 v in 36,37 2.7v + ? 1.1v v on_clk + ? sw3 lockout internal regulator and reference master oscillator 2mhz 5 run-ss2 4 fb3 8 v on sw2 lockout + 0.625v 26 27 + ? figure 1 b lock diagram
lt3513 11 3513fc the lt3513 is a highly integrated power supply ic contain - ing four separate switching regulators and a low dropout linear regulator (ldo). switching regulator 1 is a step- down 2.2a regulator with inductor current sense and an integrated boost schottky diode. switching regulator 2 can be configured as a step-up or sepic converter and has a 1.5a switch. switching regulator 3 consists of a step-up regulator with a 0.25a switch as well as an integrated schottky diode. switching regulator 4 is a negative regula - tor with a switch current limit of 0.25a and an integrated schottky diode. linear regulator 5 is capable of providing 8ma of current to the base of an external npn transistor. the regulators share common circuitry including input source, voltage reference and master oscillator. operation can be best understood by referring to the block diagram as shown in figure 1. if the run-ss1 pin is pulled to ground, the lt3513 is shut down and draws 30a from the input source tied to v in . an internal 2a current source charges the external soft- start capacitor, generating a voltage ramp at this pin. if the run-ss1 pin exceeds 0.8v, the internal bias circuits turn on, including the internal regulator, reference and 2mhz master oscillator. the master oscillator generates four clock signals, one for each of the switching regulators. switching regulator 1 will only begin to operate when the run-ss1 pin reaches 0.8v. switcher 1 generates v logic , which must be tied to the bias pin. when bias reaches 2.8v, the npns pulling down on the run-ss2 and run - ss3/4 pins turns off, allowing an internal 2a current sour ce to charge the external capacitors tied to run-ss2 and run-ss3/4 pins. when the voltage on run-ss2 reaches 0.8v, switcher 2 is enabled. correspondingly, when the voltage on run-ss3/4 reaches 0.8v, switchers 3 and 4 are enabled. av dd , e3 and v off will then begin rising at a rate determined by the capacitors tied to the run-ss2 and run-ss3/4 pins. when all four switching outputs reach 90% of their programmed voltages, the npn pulling down on the c t pin will turn off, and an internal 20a current source will charge the external capacitor tied to the c t pin. when the c t pin reaches 1.1v, the output disconnect pnp turns on, connecting v on to e3. in the event of any of the four outputs dropping below 90% of their programmed voltage, panelprotect circuitry pulls the c t pin to gnd, disabling v on . (2a) (2b) figure 2. lt3513 power-up sequence. (traces from both photos are synchnonized to the same trigger) run-ss 2v/div v logic 5v/div i l1 1a/div i l2 500a/div ss-234 2v/div av dd 10v/div pgood 20v/div 5ms/div 3513 f02a v off 10v/div v ss3/4 2v/div v ct 2v/div i l4 500ma/div i l3 500ma/div v e3 20v/div v on 20v/div 5ms/div 3513 f02b o pera t ion
lt3513 12 3513fc o pera t ion a power good comparator monitors av dd and turns on when fb2 is at or above 90% of its regulated value. the output is an open-collector transistor that is off when the output is out of regulation, allowing an external resistor to pull the pin high. this pin can be used with a p-channel mosfet that functions as an output disconnect for av dd . the four switchers are current mode regulators. instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. compared to voltage mode control, cur - rent mode control improves loop dynamics and provides cycle-by-cycle current limit. all four switchers employ a constant-frequency current mode control scheme. switcher 1, the step-down regula- tor, differs slightly from the others with inductor current sense. instead of monitoring the current at the switch, current nodes are used to measure the current through the inductor. inductor current sense does not suffer from minimum on-time problems, therefore always keep- ing the switch current limited with any input-to-output voltage ratio. switcher 1 is always synchronized to the master oscillator. the other three switchers each have their own slave oscillator. the slave oscillator reduces the frequency when the feedback voltage dips below 0.75v and decreases linearly below the threshold as shown in the performance characteristics frequency foldback plot. other than these two differences, the control loop is similar in all four switchers. a pulse from the master oscillator for switcher 1 or a pulse from the slave oscillator for the other three switchers sets the rs latch and turns on the internal npn bipolar power switch. current in the switch and the external inductor begins to increase. when this current exceeds a level determined by the voltage at v c , the current comparator resets the latch, turning off the switch. the current in the inductor flows through the schottky diode and begins to decrease. the cycle begins again at the next pulse from the oscillator. in this way, the voltage on the v c pin controls the current through the inductor to the output. the internal error amplifier regulates the output by continually adjusting the v c pin voltage. the threshold for switching on the v c pin is 0.8v, and an active clamp of 1.8v limits the v c voltage. switchers 2, 3 and 4 also contain an independent current limit not dependent on v c or duty cycle. switcher 1s current limit is controlled by the v c voltage and varies with duty cycle. all four switch- ers also use slope compensation to ensure stability with the current mode scheme at duty cycles above 50%. the run-ss1, run-ss2 and run-ss3/4 pins control the rate of rise of the feedback pins. the switch driver for sw1 operates either from v in or from the boost pin. an external capacitor and an integrated schottky diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to saturate the internal bipolar npn power switch for efficient operation. i nput v ol tage r ange s tep - down considera tion the minimum operating voltage of switcher 1 is determined either by the lt3513s undervoltage lockout of ~4v or by its maximum duty cycle. a user defined undervoltage lockout may be set with the uvlo pin at a voltage higher than the internal undervoltage lockout. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = v out + v f v in C v sw + v f where v f is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch
lt3513 13 3513fc (~0.3v at maximum load). this leads to a minimum input voltage of: v in(min) = v out + v f dc max C v f + v sw with dc max = 0.75. the user defined undervoltage is set by a resistor divider connected to the uvlo pin. the comparator pulls 3a from the pin when the uvlo pin is higher than 1.25v. the hysteresis and minimum input voltage equations are as follows: v hys = r2 + 2k ( ) ? 3.9a v in(min) = 1.25v r1 + r2 r1 current should be at least 30% higher. for highest efficiency, the series resistance (dcr) should be less than 0.1. table 1 lists several vendors and types that are suitable. table 1. inductor vendors vendor url part series type coilcraft www.coilcraft.com mss7341 shielded murata www.murata.com lqh55d open tdk www.component.tdk.com slf7045 slf10145 shielded shielded toko www.toko.com dc62cb d63cb d75c d75f shielded shielded shielded open sumida www.sumida.com cr54 cdrh74 cdrh6d38 cr75 open shielded shielded open the optimum inductor for a given application may differ from the one indicated by this simple design guide. a larger value inductor provides a higher maximum load current, and reduces the output voltage ripple. if your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple cur - rent. this allows you to use a physically smaller inductor or one with a lower dcr resulting in higher efficiency. be aware that the maximum load current depends on input voltage. a graph in the typical performance characteris - tics section of this data sheet shows the maximum load current as a function of input voltage and inductor value for v out = 3.3v. in addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technologys application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum induc- tance is required to avoid subharmonic oscillations, see application note 19. o pera t ion r2 r1 uvlo 3513 a1 v in 38 i nductor s election and m aximum o utput c urrent a good first choice for the inductor value is: l = v out + v f 1.8 where v f is the voltage drop of the catch diode (~0.4v) and l is in h. the inductors rms current rating must be greater than the maximum load current and its saturation
lt3513 14 3513fc the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. the lt3513 limits its switch cur - rent in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt3513 will deliver depends on the switch current limit, the inductor value, and the input and output voltages. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: ? i l = 1C dc ( ) v out + v f ( ) l ? f where f is the switching frequency of the lt3513 and l is the value of the inductor. the peak inductor and switch current is: i sw(pk) = i lpk = i out + ? i l 2 to maintain output regulation, this peak current must be less than the lt3513s switch current limit of i lim . for sw1, i lim is at least 2a at dc = 0.35, and decreases linearly to 1.5a at dc = 0.75 as shown in the typical performance characteristics section. the maximum output current is a function of the chosen inductor value: i out(max) = i lim C ? i l 2 = 2.5a ? 1C 0.57 ? dc ( ) C ? i l 2 choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. one approach to choosing the inductor is to start with the simple rule given above, look at the available inductors and choose one to meet cost or space goals. then use these equations to check that the lt3513 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. discontinuous operation occurs when i out is less than i l /2. o utput c ap acitor s election for 5v and 3.3v outputs, a 10f 6.3v ceramic capacitor (x5r or x7r) at the output results in very low output volt - age ripple and good transient response. other types and values will also work; the following discussion explores tradeoffs in output ripple and transient performance. the output capacitor filters the inductor current to gen- erate an output with low voltage ripple. it also stores energy in order satisfy transient loads and stabilizes the lt3513s control loop. because the lt3513 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. you can estimate output ripple with the following equations: v ripple = ? i l 8 ? f ? c out for ceramic capacitors, and v ripple = i l t43gpsfmfduspmzujddbqbdjupstuboubmvn and aluminum) where i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: i c(rms) = ? i l 12 another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: c out > 10 ? l ? i lim v out ? ? ? ? ? ? 2 o pera t ion
lt3513 15 3513fc the low esr and small size of ceramic capacitors make them the preferred type for lt3513 applications. however, not all ceramic capacitors are the same. many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied volt- age and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types. electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. tantalum and newer, lower esr organic electrolytic capacitors intended for power supply use are suitable, and the manufacturers will specify the esr. chose a capacitor with a low enough esr for the required output ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. one benefit is that the larger capacitance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. table 2. low esr surface mount capacitors vendor type series taiyo yuden ceramic x5r, x7r avx ceramic tantalum x5r, x7r tps kemet tantalum ta organic al organic t491, t494, t495 t520 a700 sanyo ta or al organic poscap panasonic al organic sp cap tdk ceramic x5r, x7r d iode s election the catch diode (d1 from figure 1) conducts current only during switch-off time. average forward current in normal operation can be calculated from: i d(avg) = i out v in C v out v in the only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current. peak reverse voltage is equal to the regulator input voltage. use a diode with a reverse voltage rating greater than the input voltage. table 3 lists several schottky diodes and their manufacturers. table 3. schottky diodes part number v r (v) i ave (a) v fat 1a (mv) v f at 2a (mv) on semiconductor mbrm120e 20 1 530 mbrm140 40 1 550 mbrs240 40 2 mbra340 40 3 450 diodes inc. b120 20 1 500 b240 40 2 500 b340a 40 3 450 b oost p in c onsiderations the minimum operating voltage of an l t3513 applica- tion is limited by the undervoltage lockout ~4v and by the maximum duty cycle. the boost circuit also limits the minimum input voltage for proper start-up. if the input voltage ramps slowly or the lt3513 turns on when the output is already in regulation, the boost capacitor may not be fully charged. because the boost capacitor charges with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages. the typical performance characteristics section shows a plot of the minimum load current to start as a function of input voltage for a 3.3v o pera t ion
lt3513 16 3513fc output. the minimum load current generally goes to zero once the circuit has started. even without an output load current, in many cases the discharged output capacitor will present a load to the switcher that will allow it to start. inverter/step-up considerations regulating positive output voltages the output voltage is programmed with a resistor divider between the output and the fb pin. choose the resistors according to: r3 = r4 v out 1.25 C 1 ? ? ? ? ? ? r4 should be 10k or less to avoid bias current errors. regulating negative output voltages the lt3513 contains an inverting op amp with a gain of 1. the nfb4 pin works just as the other fb pins. choose the resistors according to: r6 = v out ? r5 1.25 C r5 r5 should be 2.5k or less to avoid bias current errors. the duty cycle for a given application using the step-up or charge pump topology is: dc = v out C v in v out the duty cycle for a given application using the inverter or sepic is: dc = v out v in + v out the lt3513 can still be used in applications where the duty cycle, as calculated above, is greater than the maximum. however, the part must be operated in discontinuous mode so that the actual duty cycle is reduced. inductor selection table 1 lists several inductor vendors and types that are suitable to use with the lt3513. consult each manufacturer for detailed information and for their entire selection of related parts. use ferrite core inductors to obtain the best efficiency, as core losses at frequencies above 1mhz are much lower for ferrite cores than for powdered-iron units. a 10h to 22h inductor will be the best choice for most lt3513 step-up and charge pump designs. choose an inductor that can carry the entire switch current without saturating. for inverting and sepic regulators, a coupled inductor, or two separate inductors is an option. when using coupled inductors, choose one that can handle at least the switch current without saturating. if using uncoupled inductors, each inductor need only handle ap- proximately one-half of the total switch current. a 4.7h to 15h coupled inductor or two 10h to 22h uncoupled inductors will usually be the best choice for most lt3513 inverting and sepic designs. r6 r5 nfb4 3513 a2 ?v out 22 o pera t ion duty cycle range the maximum duty cycle (dc) of the lt3513 switching regulator is 75% for sw2, and 84% for sw3 and sw4.
lt3513 17 3513fc output capacitor selection use low esr (equivalent series resistance) capacitors at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small pack - ages. x7r dielectrics are preferred, followed by x5r, as these materials retain their capacitance over wide voltage and temperature ranges. a 10f to 22f output capaci- tor is sufficient for most lt3513 applications. even less capacitance is required for outputs with |v out | > 20v or |i out | < 100ma. solid tantalum or os-con capacitors will also work, but they will occupy more board area and will have a higher esr than a ceramic capacitor. always use a capacitor with a sufficient voltage rating. diode selection a schottky diode is recommended for use with the lt3513 switcher 2 and switcher 4. the schottky diode for switcher 3 is integrated inside the lt3513. choose diodes for switcher 2 and switcher 4 rated to handle an average current greater than the load current and rated to handle the maximum diode voltage. the average diode current in the step-up and sepic is equal to the load current. each of the two diodes in the charge pump configurations carries an average diode current equal to the load current. the ground connected diode in the charge pump is integrated into the lt3513. the maximum diode voltage in the step- up and charge pump configurations is equal to |v out |. the maximum diode voltage in the sepic and inverting configurations is v in + |v out |. input capacitor selection bypass the input of the lt3513 circuit with a 4.7f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type will work if there is additional bypassing provided by bulk electrolytic capacitors or if the input source impedance is low. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input sup- ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt3513 input and to force this switching current into a tight local loop, minimizing emi. the input capaci- tor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rating. the input capacitor rms current can be calculated from the step-down output voltage and current, and the input voltage: c in(rms) = i out v out v in C v out ( ) v in < i out 2 and is largest when v in = 2v out (50% duty cycle). the ripple current contribution from the other channels will be minimal. considering that the maximum load current from switcher 1 is ~3a, rms ripple current will always be less than 1.5a. the high frequency of the lt3513 reduces the energy storage requirements of the input capacitor, so that the capacitance required is less than 10f. the com - bination of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors makes them the preferred choice. the low esr results in very low voltage ripple. ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. use x5r and x7r types. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10f will be required to meet the esr and ripple current requirements. because the input capacitor is likely to see high surge currents when the input source is applied, only consider a tantalum capacitor if it has the appropriate surge current rating. the manufacturer may also recommend operation o pera t ion
lt3513 18 3513fc below the rated voltage of the capacitor. be sure to place the 1f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. a final caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the lt3513. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor (an electrolytic) in parallel with the ceramic capacitor. for details, see ap - plication note 88. soft-start and shutdown the run-ss1(run/soft-start) pin is used to place the switching regulators and the internal bias circuits in shut - down mode. it also provides a soft-start function, along with run-ss2 and run-ss3/4. if the run-ss1 pin is pulled to ground, the lt3513 enters its shutdown mode with all regulators off and quiescent current reduced to ~30a. an internal 2a current source pulls up on the run-ss1, run-ss2, and run-ss3/4 pins. if the run- ss1 pin reaches ~0.6v, the internal bias circuits start and the quiescent currents increase to their nominal levels. if a capacitor is tied from the run-ss1, run-ss2 or run - ss3/4 pins to ground, then the internal pull-up current will generate a voltage ramp on these pins. this voltage clamps the v c pin, limiting the peak switch current and therefore input current during start-up. the run-ss1 pin clamps v c1 , the run-ss2 pin clamps v c1 and the run - ss3/4 pin clamps the v c3 and v c4 pins. a good value for the soft-start capacitors is c out /10,000, where c out is the value of the largest output capacitor. v on pin considerations the v on pin is the delayed output for switching regulator 3. when the c t pin reaches 1.1v, the output disconnect pnp turns on, connecting v on to e3. the v on pin is current limited and will protect the lt3513 and input source from a shorted output. the v on pin output is also controlled from the v on_clk pin. when v on_clk is low, the v on output will turn on if the c t pin is greater than 1.1v. when v on_clk is high, greater than 1.5v, the v on output is disabled and the v onsink open collector device turns on. if the v onsink pin is connected to v on through a resistor, the v on voltage will decay with a high v on_clk . v on_clk may be synced to the horizontal scanning frequency to improve lcd image quality. low voltage dropout linear regulator the lt3513 features an output to drive an external npn transistor ldo to provide a lower voltage logic supply volt- age. the output is capable of providing 10ma of current to the base of the npn. the output of the ldo is controlled by the fb5 pin. choose the resistor values according to: r8 = r7 v ldo 0.625v C 1 ? ? ? ? ? ? r8 should be 10k or less to avoid bias current errors. the internal compensation of the ldo relies on a low esr ceramic capacitor between the values of 2.2f and 20f. x7r dielectrics are preferred, followed by x5r, as these materials retain their capacitance over wide voltage and temperature ranges. printed circuit board layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 3 shows the high current paths in the step-down regula- tor cir cuit. note that in the step-down regulators, large, switched currents flow in the power switch, the catch diode and the input capacitor. in the step-up regulators, large, switched currents flow through the power switch, the switching diode and the output capacitor. in sepic and o pera t ion
lt3513 19 3513fc inverting regulators, the switched currents flow through the power switch, the switching diode and the tank capaci- tor. the loop formed by the components in the switched current path should be as small as possible. place these components, along with the inductor and output capacitor, on the same side of the circuit board, and connect them on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c2. additionally, keep the sw and boost nodes as small as possible. thermal considerations the pcb must provide heat sinking to keep the lt3513 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these lay- ers will spread the heat dissipated by the lt3513. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 25c or less. with 100lfpm airflow, this resistance can fall by another 25%. further increases in airflow will lead to lower thermal resistance. v in sw gnd (3a) v in v sw c1 d1 c2 3519 f03 l1 sw gnd (3c) v in sw gnd (3b) i c1 figure 3. subtracting the current when the switch is on (3a) from the current when the switch is off (3b) reveals the path of the high frequency switching current (3c) keep this loop small. the voltage on the sw and boost nodes will also be switched; keep these nodes as small as possible. finally, make sure the circuit is shielded with a local ground plane figure 4. topside pcb layout o pera t ion
lt3513 20 3513fc uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer p ackage descrip t ion
lt3513 21 3513fc information furnished by linear technology c orporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology c orporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 01/11 revised uvlo pin hysteresis current and switch 2 current limit max values in electrical characteristics section 3 (revision history begins at rev c)
lt3513 22 3513fc linear technology corporation 1630 mc c arthy blvd., milpitas, c a 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com linear technology corporation 2008 lt 0111 rev c ? printed in usa r ela t e d p ar t s part number description comments lt3003 3-channel led ballaster with pwm dimming v in : 3v to 48v, i q = 3,000:1 true color pwm?, i sd < 5a, msop10 package lt3465/lt3465a constant current, 1.2mhz/2.7mhz, high efficiency white led boost regulators with integrated schottky diode v in : 2.7v to 16v, v out(max) = 34v, i q = 1.9ma, i sd < 1a, thinsot? package lt3466/lt3466-1 dual constant current, 2mhz high efficiency white led boost regulators with integrated schottky diode v in : 2.7v to 24v, v out(max) = 40v, i q = 5ma, i sd < 16a, 3mm w 3mm dfn10 package lt3474 36v, 1a (i led ), 2mhz step-down led driver v in : 4v to 36v, v out(max) = 13.5v, i q = 400:1 true color pwm, i sd < 16a, tssop16e package lt3475 dual 1.5a (i led ), 36v, 2mhz step-down led driver v in : 4v to 36v, v out(max) = 13.5v, i q = 3,000:1 true color pwm, i sd < 1a, tssop20e package lt3476 quad output 1.5a, 2mhz high current led driver with 1,000:1 dimming v in : 2.8v to 16v, v out(max) = 36v, i q = 1,000:1 true color pwm, i sd < 10a, 5mm w 7mm qfn10 package lt3478/lt3478-1 42v, 4.5a (i sw ), 2.25mhz, led drivers with 3,000:1 true color pwm dimming v in : 2.8v to 36v, v out(max) = 42v, i q = 6.1ma, i sd < 3a, tssop16e package lt3486 dual 1.3a, 2mhz high current led driver v in : 2.5v to 24v, v out(max) = 36v, i q = 1,000:1 true color pwm, i sd < 1a, 5mm w 3mm dfn, tssop16e packages lt3491 constant current, 2.3mhz, high efficiency white led boost regulator with integrated schottky diode v in : 2.5v to 12v, v out(max) = 27v, i q = 2.6ma, i sd < 8a, 2mm w 2mm dfn6, sc70 packages lt3494/lt3494a 40v, 180ma/350ma micropower low noise boost converters with output disconnect v in : 2.3v to 16v, v out(max) = 40v, i q = 65a, i sd < 1a, 3mm w 2mm dfn8 package lt3497 dual 2.3mhz, full function led driver with integrated schottkys and 250:1 true color pwm dimming v in : 2.5v to 10v, v out(max) = 32v, i q = 6ma, i sd < 12a, 3mm w 2mm dfn10 package lt3498 2.3mhz, 20ma led driver and oled driver with integrated schottkys v in : 2.5v to 12v, v out(max) = 32v, i q = 1.65ma, i sd < 9a, 3mm w 2mm dfn12 package lt3591 constant current, 1mhz, high efficiency white led boost regulator with integrated schottky diode and 80:1 true color pwm dimming v in : 2.5v to 12v, v out(max) = 40v, i q = 4ma, i sd < 9a, 3mm w 2mm dfn8 package lt3595 16-channel 48v, 2mhz buck mode led driver with 3000:1 true color pwm dimming v in : 4.5v to 50v, i q = 3,000:1 true color pwm, i sd < 3a, 5mm w 9mm qfn56 package

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